DocumentCode
2407120
Title
Precise thickness control for ultra-thin SOI in ELTRAN® SOI-Epi™ wafer
Author
Sato, N. ; Kakizaki, Y. ; Atoji, T. ; Notsu, K. ; Miyabayashi, H. ; Ito, M. ; Yonehara
Author_Institution
ELTRAN Bus. Center, Canon Inc., Kanagawa, Japan
fYear
2002
fDate
7-10 Oct 2002
Firstpage
209
Lastpage
210
Abstract
In ultra-thin-SOI MOSFET, especially in fully depleted operation, threshold voltage is strongly affected by SOI thickness in addition to dopant concentration. For instance, 5 % of tolerance is proposed in ITRS2001. This paper discusses the SOI thickness uniformity in various periods of undulations, especially focusing on ELTRAN SOI-Epi wafers, that is formed by bonding of epitaxial layer on porous Si, splitting, etching back of porous Si, and final Hz annealing to smooth the SOI surface.
Keywords
MOSFET; annealing; semiconductor epitaxial layers; silicon-on-insulator; thickness control; ELTRAN; annealing; epitaxial layer; etching back; fully depleted operation; thickness control; thickness uniformity; threshold voltage; ultra-thin-SOI MOSFET; Annealing; MOSFETs; Semiconductor epitaxial layers; Silicon on insulator technology; Thickness control;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference, IEEE International 2002
Print_ISBN
0-7803-7439-8
Type
conf
DOI
10.1109/SOI.2002.1044479
Filename
1044479
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