DocumentCode
2407154
Title
A Generic Approach for Digital Clock Synthesis Used for HDTV/PC-VGA Receiver
Author
Pietrzyk, Michael ; Koellmann, Andreas ; Simons, Sven
Author_Institution
NXP Semicond. GmbH, Hamburg
fYear
2008
fDate
9-13 Jan. 2008
Firstpage
1
Lastpage
2
Abstract
This paper presents a new approach for PLL based generation of clock signals. The idea is to provide a generic solution that can serve a wide scope of applications. The novel architecture provides virtually unconstraint temporal resolution. The partitioning between analog and digital building blocks enables easy transfer to fast developing CMOS process technologies.
Keywords
CMOS integrated circuits; clocks; digital phase locked loops; high definition television; television receivers; CMOS process technologies; HDTV/PC-VGA receiver; PLL; analog building blocks; clock signals; digital building blocks; digital clock synthesis; temporal resolution; Clocks; Distributed control; Frequency; HDTV; Phase locked loops; Signal processing; Signal resolution; Signal synthesis; System-on-a-chip; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Consumer Electronics, 2008. ICCE 2008. Digest of Technical Papers. International Conference on
Conference_Location
Las Vegas, NV
Print_ISBN
978-1-4244-1458-1
Electronic_ISBN
978-1-4244-1459-8
Type
conf
DOI
10.1109/ICCE.2008.4588042
Filename
4588042
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