DocumentCode :
2407264
Title :
A unified method to handle different kinds of placement constraints in floorplan design
Author :
Young, Evangeline F Y ; Chu, Chris C N ; Ho, M.L.
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of Hong Kong, China
fYear :
2002
fDate :
2002
Firstpage :
661
Lastpage :
667
Abstract :
In floorplan design, it is common that a designer will want to control the positions of some modules in final packing for various purposes such as data path alignment, I/O connection, etc.. There are several previous works (Young and Wong, 1998 and 1999; Young et al, 1999; Murata et al, 1997; Chang et al, 2000) focusing on a few particular kinds of placement constraint. In this paper, we present the first "unified method" to handle all of them simultaneously, including pre-placed constraint, range constraint, boundary constraint, alignment, abutment and clustering, etc., in general nonslicing floorplans. We have used incremental updates and an interesting reduced graphs idea to improve the runtime of the algorithm. We tested our method using some benchmark data with about one eighth of the modules having placement constraints and the results are very promising. Good packing with all the constraints satisfied can be obtained efficiently
Keywords :
VLSI; circuit layout CAD; integrated circuit interconnections; integrated circuit layout; modules; I/O connection; abutment; algorithm runtime; alignment; benchmark data; boundary constraint; clustering; data path alignment; final packing; floorplan design; module positions; nonslicing floorplans; packing constraints; placement constraint; placement constraints; placement constraints handling; pre-placed constraint; range constraint; reduced graphs; unified method; Benchmark testing; Circuit optimization; Circuit testing; Clustering algorithms; Computer science; Data engineering; Design engineering; Design optimization; Runtime; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings.
Conference_Location :
Bangalore
Print_ISBN :
0-7695-1441-3
Type :
conf
DOI :
10.1109/ASPDAC.2002.995011
Filename :
995011
Link To Document :
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