Title :
A partitioning and storage based built-in test pattern generation method for scan circuits
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
We describe a built-in test pattern generation method for scan circuits. The method is based on partitioning and storage of test sets. Under this method, a precomputed test set is partitioned into several sets containing values of different primary inputs or state variables. The on-chip test set is obtained by implementing the Cartesian product of the various sets. The sets are reduced as much as possible before they are stored on-chip in order to reduce the storage requirements and the test application time
Keywords :
automatic test pattern generation; built-in self test; combinational circuits; fault simulation; logic partitioning; Cartesian product; ISCAS-89 benchmark circuits; ITC-99 benchmark circuits; built-in test pattern generation method; combinational circuit; full-scan circuits; on-chip test set; partitioning; precomputed test set partitioning; primary inputs; scan circuits; state variables; storage requirements; test application time; test set storage; Built-in self-test; Circuit faults; Circuit testing; Cities and towns; Combinational circuits; Counting circuits; Encoding; Sequential analysis; Sequential circuits; Test pattern generators;
Conference_Titel :
Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings.
Conference_Location :
Bangalore
Print_ISBN :
0-7695-1441-3
DOI :
10.1109/ASPDAC.2002.995013
