Title :
Evaluation of statistical outlier rejection methods for IDDQ limit setting
Author :
Sabade, Sagar ; Walker, H.
Author_Institution :
Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
Abstract :
The quiescent current testing (IDDQ testing) for CMOS ICs provides several advantages over other testing methods. However, the future of I DDQ testing is threatened by increased sub-threshold leakage current for new technologies. The conventional pass/fail limit setting methodology cannot survive in its present form. In this paper we evaluate two statistical outlier rejection methods - the Chauvenet´s criterion and the Tukey test - for their applicability to IDDQ testing. They are compared with the static-threshold method The results of the analysis of application of these methods to the SEMATECH data are presented
Keywords :
CMOS integrated circuits; VLSI; integrated circuit testing; leakage currents; normal distribution; statistical analysis; CMOS ICs; Chauvenet criterion; IDDQ limit setting; Tukey test; quiescent current testing; static-threshold method; statistical outlier rejection methods; subthreshold leakage current; Very large scale integration;
Conference_Titel :
Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings.
Conference_Location :
Bangalore
Print_ISBN :
0-7695-1441-3
DOI :
10.1109/ASPDAC.2002.995024
