Evaluation of statistical outlier rejection methods for IDDQ limit setting

The quiescent current testing (IDDQ testing) for CMOS ICs provides several advantages over other testing methods. However, the future of I _DDQ testing is threatened by increased sub-threshold leakage current for new technologies. The conventional pass/fail limit setting methodology cannot survive in its present form. In this paper we evaluate two statistical outlier rejection methods - the Chauvenet´s criterion and the Tukey test - for their applicability to IDDQ testing. They are compared with the static-threshold method The results of the analysis of application of these methods to the SEMATECH data are presented