DocumentCode :
2407604
Title :
Challenges in the design of a scalable data-acquisition and processing system-on-silicon
Author :
Karanth, S. ; Sarkar, Soujanna ; Venkatraman, R. ; Jagini, Shyam S. ; Venkatesh, N. ; Rao, Jagdish C. ; Udayakumar, H. ; Manohar, S. ; Sheshadri, K.P. ; Talapatra, Somsubhra ; Mhatre, Parag ; Abraham, Jais ; Parekhji, Rubin
Author_Institution :
Texas Instruments India Ltd., Bangalore, India
fYear :
2002
fDate :
2002
Firstpage :
781
Lastpage :
788
Abstract :
Increasing complexity of the functionalities and the resultant growth in number of gates integrated in a chip coupled with shrinking geometries and short cycle time requirements bring several challenges into the design of present day VLSI chips. We present the challenges faced and the approaches successfully adopted in the design of a complex 2.5 million gate high bandwidth data acquisition and processing VLSI chip (a trace-receiver chip, code-named Drishti) in a deep sub-micron technology at Texas Instruments India. The very high design complexity arises due to the rich architecture of the trace-receiver chip, the aggressive timing and performance requirements and its large size. The trace-receiver chip is highly configurable and scalable, thereby catering to both low-end systems, which are cost sensitive, and high-end applications. Efficient logical and physical partitioning, design reuse and DFT strategies are a few of the techniques that were applied in this design. We present these along with details on the various analyses carried out as part of the design, including signal-integrity, reliability and system-level analyses, which were very critical in ensuring design-closure
Keywords :
VLSI; application specific integrated circuits; data acquisition; design for testability; digital signal processing chips; integrated circuit reliability; logic partitioning; microcontrollers; timing; DFT; Drishti; Texas Instruments India; VLSI; cycle time requirements; deep sub-micron technology; design reuse; high-end applications; logical partitioning; low-end systems; physical partitioning; reliability; scalable data acquisition; scalable processing; signal-integrity; system-level analyses; system-on-silicon; timing requirements; trace-receiver chip; Bandwidth; Costs; Data acquisition; Face; Geometry; Instruments; Signal analysis; Signal design; Timing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings.
Conference_Location :
Bangalore
Print_ISBN :
0-7695-1441-3
Type :
conf
DOI :
10.1109/ASPDAC.2002.995028
Filename :
995028
Link To Document :
بازگشت