DocumentCode
2407622
Title
Fast method for the prediction of the capacitance of via through-holes
Author
Jegannathan, S. ; De Zutter, Daniël ; Van den Berghe, Steve
Author_Institution
Dept. of Inf. Technol., Ghent Univ., Belgium
fYear
1998
fDate
26-28 Oct 1998
Firstpage
140
Lastpage
143
Abstract
In this paper, a fast method for the prediction of the excess capacitance of vias is proposed. The effect of the connecting lines is also examined. Numerical simulations verify the validity of the method proposed. The fast method leads to an upper capacitance bound that is further reduced by the presence of the connecting lines
Keywords
capacitance; circuit analysis computing; numerical analysis; printed circuit design; capacitance prediction; connecting line effects; connecting lines; numerical simulations; upper capacitance bound; via excess capacitance; via through-holes; Capacitance; Dielectric substrates; Green´s function methods; Information technology; Integral equations; Joining processes; Numerical simulation; Region 1; Region 3; Upper bound;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Performance of Electronic Packaging, 1998. IEEE 7th Topical Meeting on
Conference_Location
West Point, NY
Print_ISBN
0-7803-4965-2
Type
conf
DOI
10.1109/EPEP.1998.733924
Filename
733924
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