Low-power Digital Filter Using Optimized CSD and Pipelined AU for 24-bit Audio DAC

Author

Lee, S.Y. ; Song, Y.S. ; Cho, J.M. ; Kim, S.W.

Author_Institution

Dept. of Electron. Eng., Korea Univ., Seoul

fYear

2008

fDate

9-13 Jan. 2008

Firstpage

1

Lastpage

2

Abstract

A new optimization algorithm of the digital filter over the CSD coefficient is proposed. This method is based on the selective weighting method assigning more number of operations to some coefficients which are more sensitive to the frequency response remaining total number of operations. Also, the optimized coefficient is utilized as Control-RAM and combined with the 4^th pipelined AU for the low-power implementation. The designed filter for 24-bit SigmaDelta audio DAC is fabricated with 0.18 um Samsung CMOS technology.

Keywords

CMOS integrated circuits; circuit optimisation; digital filters; digital-analogue conversion; frequency response; integrated circuit design; low-power electronics; CSD coefficient; Samsung CMOS technology; audio DAC; control-RAM; digital-to-analog converter; frequency response; low-power digital filter; optimization algorithm; optimized CSD; pipelined AU; selective weighting method; size 0.18 mum; word length 24 bit; CMOS technology; Digital filters; Digital systems; Digital-analog conversion; Finite impulse response filter; Frequency response; Gold; Hardware; Large scale integration; Optimization methods;

fLanguage

English

Publisher

ieee

Conference_Titel

Consumer Electronics, 2008. ICCE 2008. Digest of Technical Papers. International Conference on

Conference_Location

Las Vegas, NV

Print_ISBN

978-1-4244-1458-1

Electronic_ISBN

978-1-4244-1459-8

Type

conf

DOI

10.1109/ICCE.2008.4588072

Filename

4588072