Combining CORDIC algorithm and FPGA to design dual core FFT processor

In this paper, the design for a dual core FFT processor based on CORDIC algorithm is presented. This design extracts the 2-base successions as the foundation, takes the FFT butterfly-shaped arithmetical unit as the object, uses the CORDIC algorithm superiority in the vector computation to simply the revolving factor calculation, and employs the assembly line technology to enhance the turnover rate for the whole system. This FFT processor has many characteristics with the simple hardware architecture, flexible disposition, low component coupling, high precision and stable running, can perform the high speed fixed-point real-time FFT operation. Experiment carried on the gate level simulation in Altera chip EP2C35F672C6 shows that this design can satisfy the 50 MHz system clock.