A Low Power SOC Architecture for The V2.0+EDR Bluetooth

This paper presents a low power SOC architecture for the v2.0+EDR (enhanced data rate) Bluetooth SOC and its applications. Our design includes a link controller, modem, RF transceiver, sub-band codec (SBC), Expended Instruction Set Computer (ESIC) processor and peripherals. According to increasing mobile applications, power consumption is more important features. To reduce power consumption, we use a reduction of data transfer using dual-port memory, clock management unit and a clock gated approach. This Chip occupies a die size of 30 mm² in CMOS 0.18 um. The current consumption of the total chip is 54 mA.