Summary of a distributed control algorithm for a dynamically reconfigurable array architecture

An array architecture composed of two hyperplanes is described. The execution plane is constructed using polymorphic processing elements and a programmable, switch-controlled, reconfigurable interconnection network. The control of the processing plane is accomplished by using a smaller hyperplane composed of small processing elements and a two-dimensional mesh interconnection scheme. The control plane cells have the capability of determining from a single seed the global configuration of the array, and of determining the size of the fault-free area surrounding each cell. Once the size of this area is determined, the size necessary for the executing algorithm can be determined, and the state pattern generated in an area with sufficient size. Reconfiguration elements in the control plane make it possible to have local reconfiguration around faulty cells, and to increase the fault-free area adjacent to a cell by isolating faulty cells. The discussion is limited to the local reconfiguration algorithm