Title :
A reconfigurable WSI neural network
Author :
Blayo, Francois ; Hurat, Philippe
Author_Institution :
Lab. Genie Inf., Unite Genie Mater., Grenoble, France
Abstract :
The solution presented consists of implementing the N neuron Hopfield network as a systolic square array made up of N 2 cells. Systolic arrays are well suited to wafer-scale integration (WSI). Inherent error tolerance of neural networks facilitates wafer design. However, a wafer-level reconfiguration is required to bypass faulty chips. The principle and the architecture of a switching element which provides a flexible wafer-level reconfiguration is described
Keywords :
VLSI; cellular arrays; neural nets; N neuron Hopfield network; error tolerance; faulty chips; neural network; reconfigurable; switching element; systolic square array; wafer-scale integration; Associative memory; Communication switching; Computer architecture; Neural networks; Neurons; Pattern recognition; Semiconductor device modeling; Systolic arrays; Very large scale integration; Wafer scale integration;
Conference_Titel :
Wafer Scale Integration, 1989. Proceedings., [1st] International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-8186-9901-9
DOI :
10.1109/WAFER.1989.47545
