40 Gbps SiGe pattern generator IC with variable clock skew and output levels

A single-chip 40 Gbps pattern generator design in 0.18 mum SiGe BiCMOS technology is described. An on-chip 128times128 bit RAM with an access time of 3 ns stores the data pattern. A hybrid 128:1 CMOS/ECL multiplexer increases the output data rate from the RAM to 40 Gbps. The output driver is back terminated with 50 ohms and provides programmable levels in the range -2 V to 2 V into a 50 ohm load. The pattern dependent jitter is under 1 ps at all output levels. The clock can be delayed by a programmable number of clock cycles plus a vernier delay of up to 50 ps in 0.2 ps steps. Power dissipation is up to 550 mW depending on the output amplitude and termination voltage