Title :
Systolic sorter for WSI implementation
Author :
Horiguchi, Susumu
Author_Institution :
Dept. of Inf. Sci., Tohoku Univ., Sendai, Japan
Abstract :
A hybrid scheme to solve the synchronization problem due to clock skew in VLSI is proposed. It is shown that the hybrid system is reconfigurable and suitable for wafer-scale integration (WSI) implementation. The redundancy architecture capable of fault tolerance is also proposed. The redundancy scheme based on a modified data manipulator is a powerful fault-tolerance architecture in the WSI implementation
Keywords :
VLSI; cellular arrays; clocks; digital integrated circuits; synchronisation; VLSI; WSI implementation; clock skew; fault tolerance; fault-tolerance architecture; hybrid system; modified data manipulator; reconfigurable; redundancy architecture; synchronization problem; Clocks; Computer architecture; Concurrent computing; Fault tolerance; Information science; Redundancy; Sorting; Systolic arrays; Very large scale integration; Wiring;
Conference_Titel :
Wafer Scale Integration, 1989. Proceedings., [1st] International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-8186-9901-9
DOI :
10.1109/WAFER.1989.47546
