DocumentCode
2408474
Title
Preliminary study of NOR digital response to single pMOSFET dielectric degradation
Author
Gorseth, T.L. ; Estrada, D. ; Kiepert, J. ; Ogas, M.L. ; Cheek, B.J. ; Price, P.M. ; Baker, R.J. ; Bersuker, G. ; Knowlton, W.B.
Author_Institution
Dept. of Electr. & Comput. Eng., Boise State Univ., ID
fYear
0
fDate
0-0 0
Lastpage
32
Abstract
The voltage-time domain (VT) characteristics of the CMOS NOR logic circuit are investigated using a switch matrix technique (SMT). VT performance is analyzed following gate oxide wearout in a pMOSFET, induced by applying a constant voltage stress (CVS) at -4.0 V. Results for the NOR VT characteristics show approximately 30% increase in rise time a considerable digression from nominal operation
Keywords
CMOS logic circuits; MOSFET; dielectric properties; logic gates; CMOS NOR logic circuit; constant voltage stress; dielectric degradation; gate oxide wearout; pMOSFET; switch matrix technique; voltage-time domain characteristics; CMOS logic circuits; Degradation; Dielectrics; Logic circuits; MOSFET circuits; Performance analysis; Surface-mount technology; Switches; Switching circuits; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics and Electron Devices, 2006. WMED '06. 2006 IEEE Workshop on
Conference_Location
Boise, ID
Print_ISBN
1-4244-0374-X
Type
conf
DOI
10.1109/WMED.2006.1678294
Filename
1678294
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