DocumentCode
2408520
Title
Increasing TLB reach with multiple pages size subblocks
Author
Park, Cheol Ho ; Park, Daeyeon
Author_Institution
Software center, Samsung Electron. Co. Ltd., Seoul, South Korea
fYear
2002
fDate
2002
Firstpage
123
Lastpage
130
Abstract
While superpages are an efficient solution to increase TLB reach, strong requirements for using superpages hinder an actual utilization. Subblock TLBs release some of these requirements and thus increase the actual utilization of superpages by attaching afield per subblock (or base page) in a superpage. On the other hand, its superpage size is strongly restricted because the number of attached fields should be the same with the superpage size in base page unit. We propose VS-TLBs (Variable-size Subblock TLB), which extend subblock TLBs to allow a subblock to be multiple base pages, while the subblock size in subblock TLBs is a base page. Therefore, with the same number of the attached fields, the TLB reach of VS-TLBs becomes much larger than subblock TLBs. By virtue of the increased TLB reach, the number of TLB misses are reduced considerably. We propose two system configurations: VS-TLB alone and VS-hybrid. VS-hybrid replaces the subblock TLB with VS-TLB in the hybrid scheme of the subblock TLB and the shadow memory. The simulation results show that the two proposed configurations reduce 52% and 67% of TLB misses from the results of their parent systems
Keywords
buffer storage; storage management; TLB reach; VS-TLB; VS-hybrid; simulation results; superpages; system configurations; translation lookaside buffer; variable-size subblock TLB; Acceleration; Application software; Computational modeling; Computer simulation; Costs; Joining processes; Physics computing;
fLanguage
English
Publisher
ieee
Conference_Titel
Performance, Computing, and Communications Conference, 2002. 21st IEEE International
Conference_Location
Phoenix, AZ
Print_ISBN
0-7803-7371-5
Type
conf
DOI
10.1109/IPCCC.2002.995143
Filename
995143
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