Title :
High-performance software emulation of 1750 A processor
Author_Institution :
Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
Abstract :
We describe a software emulator of the MIL-STD-1750 A architecture that executes 1750A code at a rate of about 4 MIPS on a Sun 200 MHz Ultra2 workstation, and effectively several times faster than that when application-specific optimizations are used. A number of optimization techniques were used, including binary translation and an unusual emulation of the 1750A timers and memory management unit. The performance technologies used within the emulator are for the most part applicable to the emulation of other processor architectures
Keywords :
aerospace computing; computer architecture; floating point arithmetic; optimisation; storage management; timing circuits; virtual machines; 1750 A processor; 4 MIPS; MIL-STD-1750 A architecture; Sun 200 MHz Ultra2 workstation; application-specific optimization; binary translation; memory management unit; optimization; performance technologies; processor architectures; software emulation; timers; Computer architecture; Cost function; Emulation; Hardware; History; Optimizing compilers; Propulsion; Software testing; Space technology; Space vehicles;
Conference_Titel :
Digital Avionics Systems Conference, 1997. 16th DASC., AIAA/IEEE
Conference_Location :
Irvine, CA
Print_ISBN :
0-7803-4150-3
DOI :
10.1109/DASC.1997.637258
