CMOS imager pixel design for space applications

Summary form only given. Our project consists of working with two existing pixel designs for a CMOS imager that will be used in space. The first pixel design consists of a standard three transistor model. The second model consists of seven transistors and incorporates correlated double sampling and the behavior and characteristics of this model will also be examined. The investigation of the behavior of these two designs will be carried out using WinSPICE and Silvaco simulation software. We will enhance the current models by comparing the two simulation software results to improve accuracy. In both the three and seven transistor models we are using double gated MOS transistors which allow for superior amplifier design and a higher quality pixel. A significant portion of the research directed toward efficiently connecting the second gate of each transistor. A unique feature of this pixel is the vertical integration or the stacking of the diodes with through box interconnects between the CMOS and the photodiode