Trends and requirements of future high-performance CMOS

The outlook of performance scaling in high-performance CMOS is explored by using an analytical expression for the intrinsic MOSFET delay. The historical trend of carrier virtual source velocity, as the main driver for continuous performance increase in the past, is presented and prospects of further velocity increase in future technology nodes are discussed. An optimistic scaling scenario with realistic assumptions about device geometry and electrostatics is presented and it is shown that from the 32-nm node onward the intrinsic transistor performance will not improve with device scaling unless parasitic capacitances are significantly reduced.