Advance packaging requirements for next generation microprocessors

As the demand for computing performance and density increases, the demand for packaging microprocessors is getting more complex. Computing speed and increased functionalities are achieved by reducing lithography features and increasing no. of transistors and no. metal layers. The performance is further enhanced by incorporating low K dielectric films in the die. While the semiconductor makes leaps, it creates technological challenges and in some areas approach technology barriers. In addition these evolving technical challenges are increasingly dependent on physical failure analysis to understand.This talk would summarize the challenges of bumping at reduced pitch, packaging thermo mechanical issues in packaging fragile low k films in a TCE mismatched system. Discussions on assembly challenges that result from assembling large die in laminate packages will also be described. In summary, talks would discuss the inter dependency between Silicon Technology, packaging Technology and Reliability. In addition these evolving technical solutions are increasingly dependent on physical failure analysis to understand the root cause and failure mechanisms. The talk will describe some typical failures and the solutions that could be developed by the use of physical failure analysis.