A Novel Hardware Acceleration Implementation for Parallel Finite-Difference Time-Domain Simulation

This article introduces a novel hardware acceleration technique based on Vector Arithmetic Logic Unit (VALU) built in a regular CPU for parallel Finite-Difference Time-Domain(FDTD) simulation with Convolutional Perfect Matched Layer(CPML) absorbing boundary condition (ABC), and gives an implementation on PC. The speedup ratio is 2.85. The experimental results show that this kind of acceleration technique is an efficient method for reducing the computing time of parallel FDTD simulation.