CAD-oriented equivalent circuit modeling of on-chip interconnects in CMOS technology

Author

Zheng, J. ; Tripathi, A. ; Hahm, Y.C. ; Ishii, T. ; Weisshaar, A. ; Tripathi, V.K.

Author_Institution

Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA

fYear

1998

fDate

26-28 Oct 1998

Firstpage

227

Lastpage

230

Abstract

A CAD-oriented modeling methodology for on-chip interconnects on lossy substrates in CMOS technology, which is based on quasistatic EM analysis and equivalent circuit model extraction, is presented. The frequency response of the equivalent circuit model shows good agreement with the computed quasi-static solution over the entire frequency range of interest. The model is further validated by comparison with the interconnect step response

Keywords

CMOS integrated circuits; circuit CAD; circuit analysis computing; equivalent circuits; frequency response; integrated circuit interconnections; integrated circuit metallisation; integrated circuit modelling; step response; CAD-oriented equivalent circuit modeling; CAD-oriented modeling methodology; CMOS technology; equivalent circuit model; equivalent circuit model extraction; frequency range; frequency response; interconnect step response; lossy substrates; model validation; on-chip interconnects; quasistatic EM analysis; CMOS technology; Conductivity; Conductors; Dielectric substrates; Equivalent circuits; Frequency; Integrated circuit interconnections; Semiconductor device modeling; Silicon; Skin effect;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging, 1998. IEEE 7th Topical Meeting on

Conference_Location

West Point, NY

Print_ISBN

0-7803-4965-2

Type

conf

DOI

10.1109/EPEP.1998.733997

Filename

733997