Title :
Using line-length effects to optimize circuit-level reliability
Author_Institution :
Dept. of Mater. Sci. & Eng., MIT, Cambridge, MA
Abstract :
By taking advantage of short-line reliability improvements in circuit-level reliability analyses and in modified layout strategies, the severe reliability constraints on future interconnect technology can be significantly addressed. To do this though, the effective length of laid-out interconnect trees must be used instead of the lengths of individual segments. Recent results on the reliability of interconnect trees are reviewed, and methods for reliability optimization are suggested.
Keywords :
integrated circuit interconnections; integrated circuit reliability; optimisation; circuit-level reliability; interconnect technology; interconnect trees; line-length effects; optimization; short-line reliability; Anodes; Atomic measurements; Cathodes; Compressive stress; Current density; Electromigration; Integrated circuit interconnections; Materials reliability; Materials science and technology; Tensile stress;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2008. IPFA 2008. 15th International Symposium on the
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-2039-1
Electronic_ISBN :
978-1-4244-2040-7
DOI :
10.1109/IPFA.2008.4588155