DocumentCode
2409210
Title
Architectural yield analysis of random defects in wafer scale integration
Author
Czechowski, J. ; Rogers, E.H. ; Chung, M.-J.
Author_Institution
Gen. Electr. Corp. Res. & Dev. Center, Schenectady, NY, USA
fYear
1989
fDate
3-5 Jan 1989
Firstpage
215
Lastpage
224
Abstract
Wafer-scale integration yield concepts are examined. New models of yield are defined and their utility is shown by analyzing the architectural and topological yield of some regular structures. Yield concepts are reviewed, the idea of architectural yield is defined, a mathematical framework for studying such yield is established, and assumptions are discussed. These are applied to architectural goals involving binary tree structures
Keywords
VLSI; network topology; trees (mathematics); architectural yield; binary tree structures; mathematical framework; random defects; topological yield; wafer scale integration; yield concepts; Circuits; Computer science; Economies of scale; Fabrication; Manufacturing; Scattering; Semiconductor device modeling; Silicon; Testing; Wafer scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Wafer Scale Integration, 1989. Proceedings., [1st] International Conference on
Conference_Location
San Francisco, CA
Print_ISBN
0-8186-9901-9
Type
conf
DOI
10.1109/WAFER.1989.47552
Filename
47552
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