Investigation on the mechanism of the leakage failure between poly gate and contact in subnano technology

With the shrinkage of the transistor dimensions, the spacing between the structures become smaller and smaller. However due to the intrinsic characteristic of the CMOS device, the reduction of the operating voltage is limited. The electrical field between different structures keeps on increasing with the shrinkage of the transistor dimensions. Furthermore, many new failure modes were observed with the scaling of semiconductor device. One of them is poly gate to contact leakage. In this paper, the mechanism of the leakage failure between poly gate and the contact in subnano CMOS technology was discussed.