Systematic embedded software generation from SystemC

Author

Herrera, F. ; Posadas, H. ; Sánchez, P. ; Villar, E.

Author_Institution

TEISA Dept., Cantabria Univ., Santander, Spain

fYear

2003

fDate

2003

Firstpage

142

Lastpage

147

Abstract

The embedded software design cost represents an important percentage of the embedded-system development costs. This paper presents a method for systematic embedded software generation that reduces the software generation cost in a platform-based HW/SW codesign methodology for embedded systems based on SystemC. The goal is that the same SystemC code allows system-level specification and verification, and, after SW/HW partitioning, SW/HW co-simulation and embedded software generation. The C++ code for the SW partition (processes and process communication, including HW/SW interfaces) is systematically generated, including the user-selected embedded OS (e.g.: the eCos open source OS).

Keywords

C++ language; computer interfaces; embedded systems; formal specification; hardware-software codesign; logic partitioning; logic simulation; operating systems (computers); program verification; C++ code; HW/SW cosimulation; HW/SW partitioning; SystemC code; eCos open source OS; embedded software design costs; embedded systems; interfaces; platform-based HW/SW codesign methodology; process communication; system-level specification; systematic embedded software generation; user-selected embedded operating system; verification; Embedded software; Europe; Software testing; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition, 2003

ISSN

1530-1591

Print_ISBN

0-7695-1870-2

Type

conf

DOI

10.1109/DATE.2003.1253600

Filename

1253600