Title :
DFT for testing high-performance pipelined circuits with slow-speed testers
Author :
Nummer, Muhammad ; Sachdev, Manoj
Author_Institution :
Waterloo Univ., Ont., Canada
Abstract :
This paper presents a methodology for testing high-performance pipelined circuits with slow-speed testers. The technique uses a clock timing circuit to control data transfer in the pipeline in test mode. A clock timing circuit capable of achieving a timing resolution of 50 ps in 0.18 μm CMOS technology is presented. The design provides the ability to test the clock timing circuit itself.
Keywords :
CMOS logic circuits; VLSI; built-in self test; design for testability; logic simulation; logic testing; pipeline processing; timing circuits; 0.18 micron; CMOS VLSI; DFT; clock timing circuit; delay-fault testing; design for testability; high-performance pipelined circuits; slow-speed testers; test mode pipeline data transfer control; timing resolution; Circuit testing; Clocks; Delay; Design for testability; Flip-flops; Frequency; Pipelines; Registers; Timing; Very large scale integration;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2003
Print_ISBN :
0-7695-1870-2
DOI :
10.1109/DATE.2003.1253610
