Virtual hardware byte code as a design platform for reconfigurable embedded systems

Reconfigurable hardware will be used in many future embedded applications. Since most of these embedded systems will be temporarily or permanently connected to a network, the possibility of reloading parts of the application at run time arises. In the 90´s it was recognized that the huge variety of processors would lead to a tremendous amount of binaries for the same piece of software. For the hardware parts of all embedded system, the situation today is even worse. The Java approach, based on a Java virtual machine (JVM), was invented to solve the problem for software. In this paper, we show how the hardware parts of an embedded system can be implemented in a hardware byte code, which can be interpreted using a virtual hardware machine running on an arbitrary FPGA. Our results show that this approach is feasible and that it leads to fast, portable and reconfigurable designs, which run on any programmable target architecture.