Title :
A method of test generation for path delay faults using stuck-at fault test generation algorithms
Author :
Ohtake, Satoshi ; Ohtani, Kouhei ; Fujiwara, Hideo
Author_Institution :
Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan
Abstract :
In this paper, we propose a test generation method for non-robust path delay faults using stuck-at fault test generation algorithms. In our method, we first transform an original combinational circuit into a circuit called a partial leaf-dag using a path-leaf transformation. Then we generate test patterns using a stuck-at fault test generation algorithm for stuck-at faults in the partial leaf-dag. Finally we transform the test patterns into two-pattern tests for path delay faults in the original circuit. We prove the correctness of the approach and experimental results on several benchmark circuits show the effectiveness of it.
Keywords :
automatic test pattern generation; combinational circuits; logic testing; combinational circuits; nonrobust path delay faults; partial leaf-dag; path delay faults; path-leaf transformation; stuck-at faults; test generation method; Benchmark testing; Circuit faults; Circuit testing; Combinational circuits; Delay; Electronic equipment testing; Information science; Semiconductor device testing; Signal generators; Test pattern generators;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2003
Print_ISBN :
0-7695-1870-2
DOI :
10.1109/DATE.2003.1253625