DocumentCode
2410081
Title
A novel dual-BBHH erasing scheme to improve endurance and retention performances for localized charge trapping memories
Author
Shi, Guangjian ; Pan, Liyang ; Ritzenthaler, Romina ; Sun, Lei ; Zhang, Zhigang ; Xu, Jun
Author_Institution
Inst. of Microelectron., Tsinghua Univ., Beijing
fYear
2008
fDate
7-11 July 2008
Firstpage
1
Lastpage
3
Abstract
The mismatch of trapped electrons and holes is the main mechanism causing reliability degradation for localized charge trapping memory devices. This paper proposes a novel dual-BBHH erasing scheme to alleviate the mismatch effect, therefore improve the endurance and retention performances simultaneously.
Keywords
hole traps; semiconductor device reliability; semiconductor storage; device reliability degradation; dual-BBHH erasing scheme; localized charge trapping memory devices; trapped electrons mismatch mechanism; trapped holes mismatch mechanism; CMOS technology; Channel hot electron injection; Charge carrier processes; Degradation; Electron traps; Logic testing; Microelectronics; Spontaneous emission; Sun; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Physical and Failure Analysis of Integrated Circuits, 2008. IPFA 2008. 15th International Symposium on the
Conference_Location
Singapore
Print_ISBN
978-1-4244-2039-1
Electronic_ISBN
978-1-4244-2040-7
Type
conf
DOI
10.1109/IPFA.2008.4588193
Filename
4588193
Link To Document