DocumentCode
2410105
Title
Formal semantics of synchronous SystemC
Author
Salem, Ashraf
Author_Institution
Comput. & Syst. Eng. Dept, Ain Shams Univ., Cairo, Egypt
fYear
2003
fDate
2003
Firstpage
376
Lastpage
381
Abstract
In this article, a denotational definition of a synchronous subset of SystemC is proposed. The subset treated includes modules, processes, threads, wait statement, ports and signals. We propose a formal model for SystemC delta delay. Also, we give a complete semantic definition for the language´s two-phase scheduler. The proposed semantic can constitute a base for validating the equivalence of synchronous HDL subsets.
Keywords
C++ language; formal languages; hardware description languages; logic design; logic simulation; processor scheduling; programming language semantics; software libraries; C++ classes; SystemC class library; SystemC delta delay; SystemC formal semantics; VHDL; formal model; modules; ports; processes; synchronous HDL subset equivalence validation; synchronous SystemC subset denotational definition; threads; two-phase scheduler semantic definition; wait statement; Clocks; Delay; Hardware design languages; Libraries; Logic functions; Production; Scheduling; Signal processing; Signal synthesis; Yarn;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe Conference and Exhibition, 2003
ISSN
1530-1591
Print_ISBN
0-7695-1870-2
Type
conf
DOI
10.1109/DATE.2003.1253637
Filename
1253637
Link To Document