Title :
Layout Parameter Analysis of a CMOS LSI
Author_Institution :
Stand. Telecommun. Labs., Harlow, UK
Abstract :
Description of computer program to verify that design requirements for speed were met by the custom layout of an oxide isolated CMOS LSI.
Keywords :
CMOS integrated circuits; electronic engineering computing; integrated circuit design; large scale integration; computer program; layout parameter analysis; oxide isolated CMOS LSI; CMOS logic circuits; CMOS process; Capacitance; Large scale integration; Layout; Logic design; Logic devices; Logic gates; Silicon; Telecommunication computing;
Conference_Titel :
Solid State Circuits Conferene, 1980. ESSCIRC 80. 6th European
Conference_Location :
Grenoble
DOI :
10.1109/ESSCIRC.1980.5468736
