DocumentCode :
2410307
Title :
A dynamically reconfigurable asynchronous processor for low power applications
Author :
Fawaz, K.A. ; Arslan, T. ; Khawam, S. ; Muir, M. ; Nousias, I. ; Lindsay, I. ; Erdogan, A.
Author_Institution :
Sch. of Eng., Univ. of Edinburgh, Edinburgh, UK
fYear :
2010
fDate :
26-28 Oct. 2010
Firstpage :
76
Lastpage :
83
Abstract :
There is an increasing demand in high-throughput mobile applications for programmability and energy efficiency. Conventional mobile Central Processing Units (CPUs) and Very Long Instruction Word (VLIW) processors cannot meet these demands. In this paper, we present a novel dynamically reconfigurable processor that targets these requirements. The processor consists of a heterogeneous array of coarse grain asynchronous cells. The architecture maintains most of the benefits of custom asynchronous design, while also providing programmability via conventional high-level languages. When compared to an equivalent synchronous design, our processor results in a power reduction of up to 18%. Additionally, our processor delivers considerably lower power consumption when compared to a market leading VLIW and a low-power ARM processor, while maintaining their throughput performance. Our processor resulted in a reduction in power consumption over the ARM7 processor of around 9.5 times when running the bilinear demosaicing algorithm at the same throughput.
Keywords :
asynchronous circuits; microprocessor chips; multiprocessing systems; reconfigurable architectures; reduced instruction set computing; VLIW processor; bilinear demosaicing algorithm; coarse grain asynchronous cells; custom asynchronous design; equivalent synchronous design; high-level languages; high-throughput mobile applications; low-power ARM processor; low-power applications; mobile central processing unit processor; programmability; reconfigurable asynchronous processor; very long instruction word processor; Arrays; Delay; Integrated circuit interconnections; Resource management; Synchronization; Wires; Asynchronous logic circuits; Reconfigurable architectures;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design and Architectures for Signal and Image Processing (DASIP), 2010 Conference on
Conference_Location :
Edinburgh
Print_ISBN :
978-1-4244-8734-9
Electronic_ISBN :
978-1-4244-8733-2
Type :
conf
DOI :
10.1109/DASIP.2010.5706249
Filename :
5706249
Link To Document :
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