A hybrid dual-core Reconfigurable Processor for EBCOT tier-1 encoder in JPEG2000 on next generation of digital cameras

In this paper, we present a JPEG2000 EBCOT tier-1 encoder based on a hybrid dual-core processor composed of a coarse-grained Dynamically Reconfigurable Processor (DRP) and an ARM core targeting next generation of cameras. The complete EBCOT tier-1 encoder is partitioned into two tasks and mapped onto the two cores respectively according to different potentials of the two processors. A Partial Parallel Architecture (PPA) for the Context Modeling (CM) is employed which can be easily tailored for DRP implementation for higher performance. The Arithmetic Encoder (AE) has been optimized as well, with a shared Dual-Port RAM (DPRAM) acting as the communication intermediate between the two cores. For the entire application, the two tasks can be pipelined via the global DPRAM for better performance. Simulation results show that the resulting architecture provides throughput reaching up to 40fps for a 256×256 8-bit grayscale standard Lena test image and shows its advantage compared with some DSP&VLIW applications. In addition, this hybrid processor also shows its high potential for implementing the complete JPEG2000 encoder on it targeting next generation of camera applications.