Partition and global methodologies for IC, package and board co-simulation In SiP applications

This paper presents a global IC-package-board co- simulation methodology for SiP (system-in-package) applications. The proposed methodology, using internal ports (auxiliary sources) concept, is applied to a real-word NXP- Semiconductor SiP test carrier built in Cadence SiP and optimal SiP-tooling environments. The obtained global simulation results, for identified complete multi-level IC-package-board sensitive path, are compared to partition-based approach for frequencies up to 20GHz. The partition-methodology is validated through careful comparison with measurement, and EM simulations for the analysis of SiP multi-conductor off-chip passive circuitry and on-chip functional components (baluns, harmonic filters). The limits of cascade-based approaches are investigated in reference to a global IC-package-board co-simulation methodology.