An Efficient Reconfigurable Image Compression Architecture

Author

Perumal, D. Ulagalandha ; Kumar, S. Arun ; Prasanth, S. ; Kumar, P. Vasantha ; Kannan, M. ; Vaidehi, V.

Author_Institution

Madras Inst. of Technol., Anna Univ., Chennai

fYear

2007

fDate

22-24 Feb. 2007

Firstpage

265

Lastpage

269

Abstract

This paper describes the development of a novel image compression architecture on runtime reconfigurable FPGAs. The partially reconfigurable discrete cosine transform architecture (PRDCT) is implemented by creating a difference bit stream between two possible architectures using flexible multiplier and accumulator (MAC) units. The non-reconfigurable modules make use of a multiplexed bus system to communicate with the reconfigurable modules. This scheme helps the user achieve significant reduction in area and power during run-time

Keywords

discrete cosine transforms; field programmable gate arrays; image coding; multiplexing equipment; MAC; PRDCT; bit stream; discrete cosine transform architecture; image compression architecture; multiplexed bus system; multiplier-accumulator units; partial reconfiguration; runtime reconfigurable FPGAs; Costs; Discrete cosine transforms; Discrete transforms; Field programmable gate arrays; Hardware; Image coding; Karhunen-Loeve transforms; Routing; Runtime; Switches; DCT; Reconfigurability; Virtex Architecture and Partial Reconfiguration;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing, Communications and Networking, 2007. ICSCN '07. International Conference on

Conference_Location

Chennai

Print_ISBN

1-4244-0997-7

Electronic_ISBN

1-4244-0997-7

Type

conf

DOI

10.1109/ICSCN.2007.350743

Filename

4156625