A 400-Gb/s and Low-Power Physical-Layer Architecture for Next-Generation Ethernet

Author

Kono, Masashi ; Kanbe, Akihiro ; Toyoda, Hidehiro

Author_Institution

Central Res. Lab., Hitachi Ltd., Hitachi, Japan

fYear

2011

fDate

5-9 June 2011

Firstpage

1

Lastpage

6

Abstract

A new 400-Gb/s (100-Gb/s×4) physical-layer architecture for the next-generation Ethernet-using 100-Gb/s serial (optical single wavelength) transmission-is proposed. For the next-generation 400-Gb/s Ethernet, there are additional requirements from the market, such as power reduction and further compactization in addition to attaining even higher transmission speed. To meet these requirements, a 100-Gb/s×4 physical-layer architecture is proposed. This architecture uses a 100-Gb/s serial (optical single wavelength) transmission Ethernet and low-power control technologies, which include transmission-capacity-degeneracy control for multi-lane transmission Ethernet. These technologies were implemented on a 100-Gb/s serial (optical single wavelength) transmission Ethernet using a field-programmable gate array (FPGA). Experimental evaluation of this implementation demonstrates the feasibility of low-power and fault-tolerant 400-Gb/s Ethernet.

Keywords

fault tolerant computing; field programmable gate arrays; next generation networks; optical fibre LAN; power control; wireless LAN; bit rate 100 Gbit/s; fault tolerant Ethernet; field programmable gate array; high transmission speed; low power control technology; low power physical layer architecture; multilane transmission Ethernet; next generation Ethernet; serial transmission Ethernet; transmission capacity degeneracy control; Adaptive optics; Integrated optics; Optical fibers; Optical switches; Physical layer;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications (ICC), 2011 IEEE International Conference on

Conference_Location

Kyoto

ISSN

1550-3607

Print_ISBN

978-1-61284-232-5

Electronic_ISBN

1550-3607

Type

conf

DOI

10.1109/icc.2011.5962750

Filename

5962750