• DocumentCode
    2410878
  • Title

    An 18K Bipolar Dynamic Random Access Memory Chip

  • Author

    Penoyer, R.F. ; El Kareh, B. ; Houghton, R.J. ; Lane, P.K. ; Selfridge, T.A.

  • Author_Institution
    Gen. Technol. Div., IBM, Essex Junction, VT, USA
  • fYear
    1980
  • fDate
    22-25 Sept. 1980
  • Firstpage
    164
  • Lastpage
    166
  • Abstract
    A 2K × 9 bipolar dynamic random access memory (RAM) experimental chip is described with a 75ns and 300ns access and cycle time, respectively. The design is based on a two device cell of 800μm size and all chip input and output signals are TTL compatible.
  • Keywords
    bipolar memory circuits; random-access storage; TTL compatible; bipolar dynamic random access memory chip; time 300 ns; time 75 ns; Art; Capacitance; Costs; DRAM chips; FETs; Logic devices; Read-write memory; Semiconductor memory; Signal design; Thyristors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid State Circuits Conferene, 1980. ESSCIRC 80. 6th European
  • Conference_Location
    Grenoble
  • Type

    conf

  • DOI
    10.1109/ESSCIRC.1980.5468765
  • Filename
    5468765
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2410878