Title :
A 10ns Bipolar Memory, Working with 18 I/O Bus
Author_Institution :
IBM-FRANCE Essonnes Component Dev., Corbeil-Essonnes, France
Abstract :
A double 576 bits random access memory organized as 2×32 words by 18 bits has been designed, completely tested, and qualified from a functionality and reliability point of view. The two major advantages of this memory are a good speedpower trade off for this particular type of organization and its ability to work with two independant 18 bits I/O busses.
Keywords :
circuit reliability; random-access storage; I-O bus; bipolar memory; random access memory; reliability point; time 10 ns; word length 18 bit; word length 576 bit; Clamps; Decoding; Driver circuits; Power supplies; Random access memory; Read-write memory; Resistors; Schottky barriers; Testing; Voltage;
Conference_Titel :
Solid State Circuits Conferene, 1980. ESSCIRC 80. 6th European
Conference_Location :
Grenoble
DOI :
10.1109/ESSCIRC.1980.5468766
