Title :
CMOS/SOS 16-Bit Parallel Multiplier and Adder-Subtractor
Author_Institution :
GEC Hirst Res. Centre, Wembley, UK
Abstract :
Two high performance CMOS/SOS devices for use in digital signal processing applications are described: a 16-bit parallel multiplier featuring a novel logic implementation and a 3 × 8-bit adder-subtractor circuit.
Keywords :
CMOS integrated circuits; adders; digital signal processing chips; CMOS-SOS parallel multiplier; adder-subtractor; digital signal processing applications; logic implementation; word length 16 bit; Adders; CMOS digital integrated circuits; CMOS logic circuits; CMOS process; CMOS technology; Delay; Digital signal processing; Latches; Logic devices; Signal processing algorithms;
Conference_Titel :
Solid State Circuits Conferene, 1980. ESSCIRC 80. 6th European
Conference_Location :
Grenoble
DOI :
10.1109/ESSCIRC.1980.5468771
