Title :
Exploiting the routing flexibility for energy/performance aware mapping of regular NoC architectures
Author :
Hu, Jingcao ; Marculescu, Radu
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Abstract :
In this paper we present an algorithm which automatically maps the IPs onto a generic regular Network on Chip (NoC) architecture and constructs a deadlock-free deterministic routing function such that the total communication energy is minimized. At the same time, the performance of the resulting communication system is guaranteed to satisfy the specified constraints through bandwidth reservation. As the main contribution, we first formulate the problem of energy/performance aware mapping, in a topological sense, and show how the routing flexibility can be exploited to expand the solution space and improve the solution quality An efficient branch-and-bound algorithm is then described to solve this problem. Experimental results show that the proposed algorithm is very fast, and significant energy savings can be achieved. For instance, for a complex video/audio application, 51.7% energy savings have been observed, on average, compared to an ad-hoc implementation.
Keywords :
circuit layout CAD; digital signal processing chips; integrated circuit layout; network routing; network topology; system-on-chip; bandwidth reservation; branch-and-bound algorithm; deadlock-free deterministic routing function; energy savings; energy/performance aware mapping; generic regular Network on Chip architecture; regular NoC architectures; routing flexibility; solution quality; solution space; video/audio application; Bandwidth; Computer architecture; Digital signal processing chips; Electronic mail; Joining processes; Network-on-a-chip; Routing; System recovery; Tiles; Wires;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2003
Print_ISBN :
0-7695-1870-2
DOI :
10.1109/DATE.2003.1253687