Title :
MRPF: an architectural transformation for synthesis of high-performance and low-power digital filters
Author :
Choo, Hunsoo ; Muhammad, Khurram ; Roy, Kaushik
Author_Institution :
Electr. & Comput. Eng. Dept., Purdue Univ., West Lafayette, IN, USA
Abstract :
We present a graph theoretical methodology that reduces the implementation complexity of a vector multiplied by a scalar The proposed approach is called MRP (minimally redundant parallel) optimization and is presented in FIR filtering framework to obtain a low-complexity multiplierless implementation. The key idea is to expand the design space using shift inclusive differential coefficients together with computation reordering using a graph theoretic approach to obtain maximal computation sharing. The transformed architecture of a filter is obtained by solving a set cover problem of the graph. A simple algorithm based on a greedy approach is presented. The proposed approach is merged with common sub-expression elimination. The simulation results show that 70% and 16% improvement in terms of computational complexity over simple implementation (transposed direct form) and common sub-expression, respectively, when using carry, lookahead adder synthesized from Synopsys designware library in 0.25 μm technology.
Keywords :
FIR filters; adders; circuit CAD; computational complexity; digital filters; graph theory; low-power electronics; parallel architectures; 0.25 micron; FIR filtering framework; MRPF; Synopsys designware library; architectural transformation; carry lookahead adder; computation reordering; computational complexity; design space; graph theoretic approach; graph theoretical methodology; greedy approach; implementation complexity; low-power digital filters; maximal computation sharing; minimally redundant parallel optimization; multiplierless implementation; set cover problem; shift inclusive differential coefficients; Computational modeling; Computer architecture; Digital filters; Digital signal processing; Filtering; Finite impulse response filter; IIR filters; Instruments; Materials requirements planning; Signal processing algorithms;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2003
Print_ISBN :
0-7695-1870-2
DOI :
10.1109/DATE.2003.1253689