DocumentCode
2411321
Title
Formalization Of VHDL Synthesis Procedure In Higher-order Logic
Author
Wang, Xinning ; Stabler, Edward P.
Author_Institution
Syracuse University
fYear
1991
fDate
28-30 Aug. 1991
Firstpage
106
Lastpage
119
Keywords
Design automation; Digital systems; Equations; Formal verification; Hardware design languages; Libraries; Logic design; Process design; Solids; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
HOL Theorem Proving System and Its Applications, 1991., International Workshop on the
Conference_Location
Davis, CA, USA
Print_ISBN
0-8186-2460-4
Type
conf
DOI
10.1109/HOL.1991.596278
Filename
596278
Link To Document