DocumentCode :
2411341
Title :
An 8kbit RAM + I/O Peripheral Circuit for Microprocessors
Author :
Horninger, K. ; Grassl, G. ; Bromme, I. ; Schwabe, U.
Author_Institution :
Siemens AG, Munich, Germany
fYear :
1980
fDate :
22-25 Sept. 1980
Firstpage :
274
Lastpage :
277
Abstract :
An 8 kbit RAM + I/O peripheral circuit for microprocessors has been realized in a scaled NMOS single-layer poly technology. Cycle time is 250 ns, counter frequency is 10 MHz, chip size is 27.6 mm2 and the supply current is approx. 200 mA, with 5 V supply voltage.
Keywords :
microprocessor chips; random-access storage; I/O peripheral; RAM; current 200 mA; frequency 10 MHz; microprocessors; peripheral circuit; scaled NMOS single-layer poly technology; time 250 ns; voltage 5 V; Counting circuits; Decoding; Energy consumption; Frequency; Latches; MOS devices; Microcomputers; Microprocessors; Random access memory; Read-write memory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid State Circuits Conferene, 1980. ESSCIRC 80. 6th European
Conference_Location :
Grenoble
Type :
conf
DOI :
10.1109/ESSCIRC.1980.5468790
Filename :
5468790
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2411341
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