CMOS varactors in NLTL pulse-compression applications

This paper discusses the feasibility of using CMOS varactors in designing all-silicon pulse-compression nonlinear transmission lines (NLTLs). Six different varactor structures based on CMOS transistors are investigated, and are divided into two groups. One group, with a monotonic C(V) characteristic, can be used in single-edge pulse-compression NLTLs, while the other, having a non-monotonic C(V), is suited for double-edge pulse-compression. After simulation and evaluation of the C_max/C_min ratios and cutoff frequencies of the six structures, two types of NMOS varactors for use in NLTL designs were fabricated in a CMOS 0.18-mum process. On-chip measurements were made. Transient simulations based on these measurements show a leading edge rise time reduction of 75% for single-edge, and 60% for double-edge pulse sharpening.