Title :
Combination of lower bounds in exact BDD minimization
Author :
Ebendt, R. ; Gunther, W.
Author_Institution :
Dept. of Comput. Sci., Kaiserslautern Univ., Germany
Abstract :
Ordered binary decision diagrams (BDDs) are a data structure for efficient representation and manipulation of Boolean functions. They are frequently used in logic synthesis and formal verification. The size of BDDs depends on a chosen variable ordering, i.e. the size may vary from linear to exponential, and the problem of improving the variable ordering is known to be NP-complete. In this paper we present a new exact branch & bound technique for determining an optimal variable order In contrast to all previous approaches, that only considered one lower bound, our method makes use of a combination of three bounds and by this avoids unnecessary computations. The lower bounds are derived by generalization of a lower bound known from VLSI design. They allow to build the BDD either top down or bottom up. Experimental results are given to show the efficiency of our approach.
Keywords :
VLSI; binary decision diagrams; circuit optimisation; computational complexity; formal verification; high level synthesis; minimisation of switching nets; NP-complete; Ordered Binary Decision Diagrams; VLSI design; bottom up; branch and bound technique; data structure; exact BDD minimization; formal verification; generalization; logic synthesis; lower bounds; top down; variable ordering; Binary decision diagrams; Board of Directors; Boolean functions; Computer science; Data structures; Formal verification; Logic; Time division multiplexing; Very large scale integration; Virtual manufacturing;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2003
Print_ISBN :
0-7695-1870-2
DOI :
10.1109/DATE.2003.1253698