Title :
MOS transistor characteristics and its dependence of plasma charging degradation on the test structure layout for a 0.13µm CMOS technology
Author :
Martin, Andreas ; Vollertsen, Rolf-Peter ; Reisinger, Hans
Author_Institution :
Central reliability Dept., Infineon Technol. AG, Neubiberg, Germany
Abstract :
The influence of interconnects and the pad stack on measured Metal-Oxide-Semiconductor (MOS) transistor parameter and their reliability degradation cannot always be neglected. The underlying effect is Plasma-Induced-Damage (PID) from the parasitic antennas connected to the MOS gate electrode. Usually, a protection diode is employed to avoid this. However, for some stress and measurement sequences a diode at the gate is not desirable. An alternative method - a layout optimisation is presented and discussed.
Keywords :
CMOS integrated circuits; MOSFET; integrated circuit interconnections; integrated circuit layout; integrated circuit reliability; CMOS technology; MOS gate electrode; MOS transistor characteristics; measurement sequences; metal-oxide-semiconductor transistor parameter; pad stack; parasitic antennas; plasma charging degradation; plasma-induced-damage; protection diode; reliability degradation; size 0.13 mum; stress sequences; test structure layout; Antenna measurements; Antennas; Logic gates; MOSFETs; Metals; Stress;
Conference_Titel :
Integrated Reliability Workshop Final Report (IRW), 2010 IEEE International
Conference_Location :
Stanford Sierra, CA
Print_ISBN :
978-1-4244-8521-5
DOI :
10.1109/IIRW.2010.5706488
