A 5-Bit Building Block for 20 MHz NMOS A/D Converters

Author

Fiedler, H. ; Hoefflinger, B. ; Demmer, W. ; Draheim, P.

Author_Institution

Univ. of Dortmund, Dortmund, Germany

fYear

1980

fDate

22-25 Sept. 1980

Firstpage

346

Lastpage

349

Abstract

This paper presents a monolithic, fully parallel 5-bit NMOS A/D converter. The chip is fabricated using a standard metal-gate enhancement/depletion technology with 7 μm minimum features. It contains 31 strobed comparators, latches, combinational logic, a 5 by 31 ROM, TTL buffers and a 4-bit DAC. This makes it a building block for two-step 8-bit converters. The chip was fully characterised at 20 megasamples per seconds. The dc linearity was better than 1/4 LSB for 80 mV step size.

Keywords

MOS integrated circuits; analogue-digital conversion; combinational circuits; comparators (circuits); digital-analogue conversion; flip-flops; integrated circuit manufacture; read-only storage; transistor-transistor logic; DAC; NMOS A/D converters; ROM; TTL buffers; building block; combinational logic; comparators; dc linearity; frequency 20 MHz; latches; size 7 mum; standard metal-gate enhancement/depletion technology; two-step converters; voltage 80 mV; word length 4 bit; word length 5 bit; word length 8 bit; CMOS technology; Circuits; Energy consumption; Latches; Linearity; Logic; MOS devices; Read only memory; Resistors; Semiconductor device measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Circuits Conferene, 1980. ESSCIRC 80. 6th European

Conference_Location

Grenoble

Type

conf

DOI

10.1109/ESSCIRC.1980.5468812

Filename

5468812