Title :
A circuit SAT solver with signal correlation guided learning
Author :
Lu, Feng ; Wang, Li-C ; Cheng, Kwang-Ting ; Huang, Ric C -y
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Abstract :
Boolean Satisfiability has attracted tremendous research effort in recent years, resulting in the developments of various efficient SAT solver packages. Based upon their design architectures, researchers have tried to develop better heuristics to further improve its efficiency, by either speeding up the Boolean Constraint Propagation (BCP) procedure or finding a better decision ordering (or both). In this paper, we propose an entirely different SAT solver design concept that is circuit-based. Our solver is able to utilize circuit topological information and signal correlations to enforce a decision ordering that is more efficient for solving circuit-based SAT problem instances. In particular, for unsatisfiable circuit examples, our solver is able to achieve from 2x up to more than 75x speedup over a state-of-the-art SAT solver.
Keywords :
Boolean algebra; circuit CAD; computability; correlation theory; learning (artificial intelligence); network topology; Boolean Constraint Propagation; Boolean satisfiability problem; SAT solver; circuit topology; decision ordering; signal correlation guided learning; Business continuity; Circuits; Design automation; Input variables; Packaging; Performance gain; Process design; Signal design; Signal processing;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2003
Print_ISBN :
0-7695-1870-2
DOI :
10.1109/DATE.2003.1253719