Impact of the storage layer charging on Random Telegraph Noise behavior of sub-50nm charge-trap-based TANOS and floating-gate memory cells

Author

Seidel, K. ; Hoffmann, R. ; Naumann, A. ; Paul, J. ; Löhr, D.A. ; Czernohorsky, M. ; Beyer, V.

Author_Institution

Fraunhofer Center Nanoelectronic Technol., Dresden, Germany

fYear

2010

fDate

17-21 Oct. 2010

Firstpage

95

Lastpage

97

Abstract

Random Telegraph Noise (RTN) characterization was performed on charge-trap-based TANOS memory cells. The analysis results of cycle stress dependence and cell size scaling are discussed based on single cell measurements. Comparing charge-trap and floating-gate memory technologies different behavior for RTN was obtained. On charge-trap cells a threshold voltage dependence and superimposed noise was observed and is discussed based on measurement results and different cell architectures.

Keywords

interface states; random noise; semiconductor device measurement; semiconductor device noise; semiconductor storage; RTN characterization; charge-trap-based TANOS memory cell; floating-gate memory cell; random telegraph noise behavior; size 50 nm; storage layer charging impact; threshold voltage; Noise; Noise measurement; Nonhomogeneous media; Nonvolatile memory; Probability; Silicon; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Reliability Workshop Final Report (IRW), 2010 IEEE International

Conference_Location

Stanford Sierra, CA

ISSN

1930-8841

Print_ISBN

978-1-4244-8521-5

Type

conf

DOI

10.1109/IIRW.2010.5706496

Filename

5706496